RISC-V Overview RISC-V (pronounced "risk-five") is an open-standard instruction set architecture (ISA) based on the established reduced instruction set computing (RISC) principles. Unlike proprietary ISAs, RISC-V is freely available for all types of use, allowing for greater flexibility and innovation in computer architecture design. The RISC-V ISA is modular, enabling implementations to be tailored to specific applications, from small embedded systems to high-performance computing. This modularity is achieved through a base integer set of instructions, with optional extensions for floating-point operations, atomic instructions, and more, making it highly adaptable.
One of the key advantages of RISC-V is its open-source nature, which fosters a collaborative ecosystem of developers, researchers, and companies. This openness eliminates licensing fees and restrictions associated with proprietary ISAs, lowering the barrier to entry for hardware and software development. Consequently, RISC-V has gained significant traction in academia, industry, and among hobbyists, leading to a diverse range of implementations and innovations. The standardisation efforts by the RISC-V Foundation ensure compatibility and interoperability among different RISC-V implementations, promoting a robust and unified ecosystem.
The simplicity and efficiency of the RISC-V design also contribute to its growing popularity. By adhering to RISC principles, RISC-V achieves a streamlined and efficient instruction set that reduces the complexity of hardware implementations. This simplicity translates to lower power consumption and higher performance, which are critical factors in embedded systems and mobile devices. Additionally, the extensibility of RISC-V allows for future enhancements and optimisations without disrupting the existing ecosystem, ensuring long-term viability and relevance in the rapidly evolving field of computer architecture.
Our RISC-VXI implementation is an advanced extension to our RISC-VX architecture, designed to push the boundaries of adaptability further. Here are some of the key features and advantages that our implementation brings:
- Vector Extensions
Implemented VxI Vector Extensions (RVV) to handle parallel data processing which is crucial for VxI workloads. These extensions allow for operations on large sets of data simultaneously, improving efficiency. - Tensor Processing
Specialised tensor processing units (TPUs), neural processing units (NPUs) and VxI ((C) JELTES Ecosystems Group, 2024) processing units. - Memory Bandwidth and Latency
Improved memory bandwidth and reduced latency to handle the large datasets typically used in VxI. Optimised memory hierarchies and the pervasive use of high-bandwidth memory (HBM). - Custom Instructions
Custom instructions with hardware support which, cumulatively, accelerate common VxI algorithms and operations, such as convolution, pooling, activation and several far more sophisticated functions. - High-Performance Interconnects
Implementation of high-speed interconnects for efficient data transfer between processors, memory, and accelerators, scaling parallel workloads across multiple processing units. - Software Ecosystem
Highly optimised compiler with deep vX / VxI integration. - Hardware-Software Co-Design
Hardware and software were co-designed to ensure that workloads are efficiently mapped to the RISCVxI architecture. This includes compilers and tracing tools which encapsulate the vX and VxI hardware foundations.